Integrated circuit including asymmetric decoupling cell and method of designing the same

An integrated circuit comprising:

• a first decoupling cell having a first height in a first direction,
• wherein the first decoupling cell comprises:
• a plurality of first P-type metal-oxide-semiconductor field effect transistors (MOSFETs) arranged in a second direction that is perpendicular to the first direction;
• and
• a plurality of first N-type MOSFETs arranged in the second direction and spaced apart from the plurality of first P-type MOSFETs in the first direction,
• wherein the plurality of first P-type MOSFETs comprises at least one first P-type decoupling MOSFET and at least one first P-type dummy MOSFET,
• wherein the plurality of first N-type MOSFETs comprises at least one first N-type decoupling MOSFET and at least one first N-type dummy MOSFET, and
• wherein a first number of the at least one first P-type decoupling MOSFET is different from a second number of the at least one first N-type decoupling MOSFET.

An integrated circuit comprising:

• at least one decoupling cell,
• wherein the at least one decoupling cell comprises:
• a first conductivity type decoupling metal-oxide-semiconductor field effect transistor (MOSFET);
• and
• a second conductivity type decoupling MOSFET, and
• a first capacitance associated with the first conductivity type decoupling MOSFET is greater than a second capacitance associated with the second conductivity type decoupling MOSFET.