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US 2022/0102328 A1Published application
Method of manufacturing a semiconductor package including a first sub-package stacked atop a second sub-package
AssigneeNanya Technology Corporation
InventorShing-Yih SHIH
Life of this patent
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Abstract
A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package.
Claims9
A method of manufacturing a semiconductor package, comprising:
- forming a first sub-package and a second sub-package, wherein forming each of the first and the second sub-package comprising following steps:
- (a) disposing at least two first semiconductor dies and a second semiconductor die disposed in between thereof on a first supporting substrate, wherein each of the first semiconductor dies comprises a plurality of through silicon vias (TSVs) substantially vertical to the first supporting substrate and each having a first end connecting to the first supporting substrate and a second end embedded in the first semiconductor die;
- (b) forming a molding layer covering the first supporting substrate, the first semiconductor dies and the second semiconductor die;
- (c) thinning the molding layer, the first semiconductor dies and the second semiconductor die, wherein the second ends of the TSVs are exposed from the first semiconductor dies, wherein upper surfaces of the TSVs, upper surfaces of the thinned molding layer, upper surfaces of the thinned first semiconductor dies and an upper surface of the thinned second semiconductor die are coplanar;
- (d) forming a bond-pad layer over the upper surfaces of the TSVs and the upper surface of the thinned second semiconductor die;
- (e) removing the first supporting substrate from lower surfaces of the TSVs, lower surfaces of the molding layer, lower surfaces of the first semiconductor dies and a lower surface of the second semiconductor die;
- and
- (f) forming a plurality of redistribution layers (RDLs) underneath the lower surfaces of the TSVs, the lower surfaces of the molding layer, the lower surfaces of the first semiconductor dies and the lower surface of the second semiconductor die;
- (g) forming a plurality of bumps connecting to the RDLs;
- and
- stacking the first sub-package atop the second sub-package by attaching the bumps of the first sub-package to the bond-pad layer of the second sub-package.
8 more elements
Dependencies are inferred from the claim text.