Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package, comprising:

• a substrate having a cavity;
• at least one semiconductor chip arranged within the cavity, and having a plurality of chip pads provided at a front surface of the semiconductor chip;
• a sealing layer covering a first surface of the substrate, and filling the cavity such that a backside surface of the semiconductor chip is exposed from the sealing layer;
• a lower redistribution wiring layer covering a second surface of the substrate opposite to the first surface, and including a plurality of first redistribution wirings electrically connected to the plurality of chip pads;
• an upper redistribution wiring layer covering the first surface of the substrate, and including a plurality of second redistribution wirings electrically connected to a plurality of connection wirings and a thermal pattern provided on the exposed backside surface of the semiconductor chip;
• and
• a plurality of outer connection members arranged on an outer surface of the lower redistribution wiring layer and electrically connected to the plurality of first redistribution wirings,
• wherein the backside surface of the semiconductor chip is coplanar with an upper surface of the sealing layer, and
• a first thickness of the thermal pattern has a value from 3 μm to 50 μm.

A semiconductor package, comprising:

• a lower redistribution wiring layer including a plurality of first redistribution wirings stacked in two levels;
• a semiconductor chip arranged on the lower redistribution wiring layer, and having a plurality of chip pads provided at a front surface to be electrically connected to the plurality of first redistribution wirings;
• a support member on the lower redistribution wiring layer to surround the semiconductor chip, and exposing a backside surface of the semiconductor chip;
• and
• an upper redistribution wiring layer on the support member, and including a plurality of second redistribution wirings electrically connected to a plurality of vertical connection structures that penetrate at least a portion of the support member, and a thermal pattern provided on the exposed backside surface of the semiconductor chip.