Semiconductor package

A semiconductor package, comprising:

• a redistribution substrate comprising a plurality of first trenches that extend through a top surface of the redistribution substrate;
• a first semiconductor chip on the redistribution substrate;
• a plurality of capacitor chips on a bottom surface of the first semiconductor chip;
• and
• an under-fill layer on the bottom surface of the first semiconductor chip,
• wherein the redistribution substrate comprises:
• a plurality of dielectric layers vertically stacked;
• a plurality of redistribution patterns in each of the plurality of dielectric layers;
• and
• a stack via between the plurality of capacitor chips,
• wherein the stack via is connected to the plurality of redistribution patterns and the first semiconductor chip.

A semiconductor package, comprising:

• a redistribution substrate comprising a plurality of first trenches that extend through a top surface of the redistribution substrate;
• a conductive terminal on a bottom surface of the redistribution substrate;
• a first semiconductor chip on the redistribution substrate, the first semiconductor chip comprising a plurality of first chip pads and a plurality of second chip pads;
• a plurality of capacitor chips on the plurality of second chip pads of the first semiconductor chip, each of the plurality of capacitor chips comprising a plurality of capacitor chip pads;
• a plurality of first connection terminals between the plurality of capacitor chips and the plurality of second chip pads;
• and
• an under-fill layer on a bottom surface of the first semiconductor chip,
• wherein the redistribution substrate comprises:
• a plurality of dielectric layers vertically stacked;
• a plurality of redistribution patterns in each of the plurality of dielectric layers, each of the plurality of redistribution patterns including a wire part and a via part;
• a plurality of upper conductive patterns, each upper conductive pattern on the wire part of a respective one of uppermost ones of the plurality of redistribution patterns and connected to the first semiconductor chip;
• a plurality of lower conductive patterns, each lower conductive pattern on the via part of a respective one of lowermost ones of the plurality of redistribution patterns and connected to the conductive terminal;
• a blocking dielectric pattern between the plurality of capacitor chips;
• and
• a stack via that penetrates the blocking dielectric pattern and is on the plurality of redistribution patterns,
• wherein the stack via is connected to the plurality of redistribution patterns and the first semiconductor chip.