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US 2022/0102280 A1Published application
Very Fine Pitch and Wiring Density Organic Side by Side Chiplet Integration
AssigneeApple Inc.
InventorsSanjay Dabral, Zhitao Cao, Kunzhong Hu
Life of this patent
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Abstract
Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.
Claims30
A package comprising:
- a die set encapsulated in a molding compound layer;
- a package-level redistribution layer (RDL) spanning across the die set and the molding compound layer and on and in electrical connection with the die set;
- wherein each die in the die set includes a die-level back end of the line (BEOL) build-up structure including a plurality of contact pads;
- and
- wherein the package-level RDL includes a plurality of die-to-die interconnects connecting the plurality of contact pads between each die and embedded within one or more photoimageable organic dielectric layers.
2 more elements
A package comprising:
- a die set encapsulated in a molding compound layer;
- an inorganic barrier layer over the die set, and between the die set and the molding compound layer;
- a package-level redistribution layer (RDL) spanning across the molding compound layer and on and in electrical connection with the die set;
- wherein the package-level RDL spans across the inorganic barrier layer laterally between dies in the die set;
- wherein each die in the die set includes a die-level back end of the line (BEOL) build-up structure including a plurality of contact pads;
- and
- wherein the package-level RDL includes a plurality of die-to-die interconnects connecting the plurality of contact pads between each die.
4 more elements
A method comprising:
- placing a die set face down on a carrier substrate;
- encapsulating the die set in a molding compound;
- removing the carrier substrate;
- measuring a location of the die set;
- comparing the measured location of the die set to a baseline location, and determining a modified wiring pattern;
- and
- forming a package-level redistribution layer (RDL) over the die sets based on the modified wiring pattern to form a plurality of die-to-die interconnects in a plurality of photoimageable polymer layers by developing permanent areas of the plurality of photoimageable polymer layers followed by dissolving undeveloped areas of the photoimageable polymer layers.
4 more elements
A chip comprising:
- a die area set formed in a same semiconductor layer;
- a back end of the line (BEOL) build-up structure formed over the die area set, the BEOL build-up structure including a plurality of contact pads;
- a chip-level redistribution layer (RDL) spanning across the BEOL build-up structure and over the die area set;
- and
- wherein the chip-level RDL includes a plurality of die area-to-die area interconnects connecting the plurality of contact pads between each die area.
2 more elements
Dependencies are inferred from the claim text.