Standard cell layout architectures and drawing styles for 5nm and beyond
AssigneeAdvanced Micro Devices, Inc.
InventorRichard T. Schultz
Life of this patent
Estimating the term…
Abstract
A system and method for efficiently creating layout for a standard cell are described. A standard cell to be used for an integrated circuit uses a full trench silicide strap as drain regions for a pmos transistor and an nmos transistor. Multiple unidirectional routes in metal zero are placed across the standard cell where each route connects to a trench silicide contact. Power and ground connections utilize pins rather than end-to-end rails in the standard cell. Additionally, intermediate nodes are routed in the standard cell with unidirectional routes.
Claims20
A standard cell layout comprising:
- a plurality of transistors;
- one or more trench silicide contacts, each formed as a source region or a drain region of a respective transistor of the plurality of transistors;
- one or more full trench silicide straps, each is a trench silicide contact formed as a drain region of two separate transistors of the plurality of transistors;
- and
- a plurality of unidirectional signal routes in a metal zero layer, wherein each route connects to a respective one of the one or more trench silicide contacts.
A method comprising:
- forming one or more trench silicide contacts, each is a trench silicide contact formed as a source region or a drain region of a respective transistor of a plurality of transistors;
- forming one or more full trench silicide straps, each is a trench silicide contact formed as a drain region of two separate transistors of the plurality of transistors;
- and
- routing a plurality of unidirectional signal routes in a metal zero layer, wherein each route connects to a respective one of the one or more trench silicide contacts.
A non-transitory computer readable storage medium storing a plurality of instructions which, when executed, generate an integrated circuit layout that comprises:
- a plurality of transistors;
- one or more trench silicide contacts, each is a trench silicide contact formed as a source region or a drain region of a respective transistor of the plurality of transistors;
- one or more full trench silicide straps, each is a trench silicide contact formed as a drain region of two separate transistors of the plurality of transistors;
- and
- a plurality of unidirectional signal routes in a metal zero layer, wherein each route connects to a respective one of the one or more trench silicide contacts.
Dependencies are inferred from the claim text.