On-chip capacitors in three-dimensional semiconductor devices and methods for forming the same

A three-dimensional (3D) semiconductor device, comprising:

• a stack of a plurality of pairs of interleaved conductive layers and first dielectric layers, wherein edges of the plurality of pairs of interleaved conductive layers and first dielectric layers are staggered;
• a pair of capacitor contacts in contact with two conductive layers of two pairs of the plurality of pairs of interleaved conductive layers and first dielectric layers, respectively;
• and
• a capacitor comprising the two conductive layers and one or more of the first dielectric layers vertically between the two conductive layers, the two conductive layers being electrically separated from one another, wherein:
• the capacitor is arranged in a dummy staircase region;
• and
• an isolation structure is adjacent to and arranged between the dummy staircase region and a core array region where a plurality of channel structures are arranged to separate the dummy staircase region and the core array region, the isolation structure comprising a dielectric stack that comprises vertically interleaved second dielectric layers and the first dielectric layers.

A method for forming a three-dimensional (3D) memory device, comprising:

• forming a memory stack comprising vertically interleaved conductive layers and first dielectric layers above a substrate;
• forming an isolation structure extending vertically through at least part of the memory stack, and being adjacent to and between a dummy staircase region where a plurality of capacitor contacts are arranged and a core array region where a plurality of channel structures are arranged to separate the dummy staircase region and the core array region and to electrically separate at least some of the conductive layers into gate electrodes in the core array region and capacitor electrodes in the dummy staircase region, the isolation structure comprising a portion of a dielectric stack that comprises vertically interleaved second dielectric layers and the first dielectric layers;
• and
• forming the plurality of capacitor contacts in contact with at least two of the capacitor electrodes in the dummy staircase region, respectively.