Selectively roughened copper architectures for low insertion loss conductive features

A system comprising:

• a microprocessor coupled to a memory within an IC package, wherein the IC package comprises a package substrate comprising:
• a metallization level within a dielectric material, wherein the metallization level comprises a plurality of conductive features each having a top surface and a sidewall surface,
• wherein the top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

A method for making a package substrate, comprising:

• forming a metallization level within a dielectric, wherein the metallization level comprises a plurality of conductive features comprising a first conductive feature and a second conductive feature, each having a top surface and a sidewall surface;
• and
• selectively roughening the plurality of conductive features to provide a first average surface roughness for the top surface of the first conductive feature and a second average surface roughness for the sidewall surface of the second conductive feature, wherein the first average surface roughness is not less than 1.5 times the second average surface roughness.