Vertically stacked transistor devices with isolation wall structures containing an electrical conductor

An integrated circuit structure, comprising:

• a lower device layer that includes a first structure comprising a first set of transistors, a first set of contact metallization, and a first set of one or more insulation isolation walls;
• an upper device layer bonded onto the lower device layer, the upper device layer includes a second structure comprising a second set of transistors, a second set of contact metallization and a second set of one or more insulation isolation walls in the upper device layer;
• and
• a power isolation wall that extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power and signals are routed between transistor devices on the upper device layer and the lower device layer.

A method of fabricating an integrated device structure comprising a vertically stacked transistor device architecture with a conducting power isolation wall, the method comprising:

• forming a vertically stacked device architecture having a lower device layer and at least a partially formed upper device layer bonded onto the lower device layer;
• forming in the lower device layer, a first structure comprising a first set of transistors, a first set of contact metallization, and a first set of one or more insulating isolation walls;
• forming in the upper device layer, a second structure comprising a second set of transistors, a second set of contact metallization, and a second set of one or more insulating isolation walls;
• masking off structures in the upper device layer with an etch resistant layer other than a particular one of the bottom insulating isolation walls in the upper device layer that is vertically aligned with a particular one of the bottom isolation walls;
• etching materials filling the particular one of the insulating isolation walls to form a cavity;
• etching materials filling the particular one of the bottom insulating isolation wall to extend the cavity from the upper device layer through the bottom device layer;
• and
• filling the cavity with a conductive metal to form the power isolation wall that routes power between the lower device layer and the upper device layer.