Semiconductor packages
AssigneeSamsung Electronics Co., Ltd.
InventorChulyong Jang
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a plurality of semiconductor chips. At least one of the semiconductor chips includes a semiconductor substrate including a semiconductor layer and a passivation layer having a third surface, a backside pad on the third surface, and a through-via penetrating through the semiconductor substrate. The backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding on one side of the electrode pad portion and surrounding a side surface of the through-via. The dam structure is spaced apart from the side surface of the through-via.
Claims20
A semiconductor package comprising:
- a plurality of semiconductor chips electrically connected to each other and stacked in a first direction,
- wherein at least one of the plurality of semiconductor chips includes:
- a semiconductor substrate including a semiconductor layer having a first surface and a second surface that are opposite each other;
- a passivation layer on the first surface and having a third surface that is opposite the first surface;
- a circuit structure on the second surface;
- a frontside pad on the circuit structure;
- a backside pad on the third surface;
- and
- a through-via in the semiconductor substrate and extending between the second surface and the third surface to be electrically connected to the backside pad and the frontside pad,
- wherein the backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding toward the first surface on one side of the electrode pad portion and surrounding a side surface of the through-via, and
- wherein the dam structure is spaced apart from the side surface of the through-via.
A semiconductor package comprising:
- at least one semiconductor chip,
- wherein the at least one semiconductor chip has an active surface and an inactive surface that are opposite each other and includes a backside pad on the inactive surface, a frontside pad on the active surface, and a through-via electrically connecting the backside pad and the frontside pad to each other,
- wherein the backside pad includes an electrode pad portion and a dam structure that extends in a first direction from the electrode pad portion toward the active surface and surrounds the through-via,
- wherein a ratio of a width of the backside pad in a second direction, horizontal to the active surface, to a width of the through-via in the second direction is within a range of about 5:1 to about 3:1, and
- wherein the dam structure is spaced apart from a side surface of the through-via.
A semiconductor package comprising:
- a first semiconductor chip including a semiconductor layer having a first surface and a second surface that are opposite each other, a passivation layer having a third surface that is opposite the first surface and a trench that is in the third surface, a through-via penetrating the semiconductor layer and the passivation layer, and a backside pad on the third surface and electrically connected to the through-via;
- a second semiconductor chip including a frontside pad and on the first semiconductor chip such that the frontside pad faces the backside pad;
- and
- a connection bump electrically connecting the backside pad and the frontside pad to each other,
- wherein the trench is spaced apart from the through-via in a first direction horizontal to the third surface,
- wherein a spacing distance between the trench and the through-via is within a range of about 2 micrometers (μm) to about 5 μm,
- wherein a ratio of a depth of the trench in a second direction, perpendicular to the third surface, to a maximum distance between the third surface and the first surface is about 0.5:1 to about 0.8:1, and
- wherein the backside pad includes a dam structure in the trench.
Dependencies are inferred from the claim text.