US 2022/0102148 A1 · GATE SPACING IN INTEGRATED CIRCUIT STRUCTURES

Abstract

Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

Claims20

Dependent claims

An integrated circuit (IC) structure, comprising:

a first gate metal having a longitudinal axis;
a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal;
a first gate contact above the first gate metal;
a second gate contact above the second gate metal;
and
an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/033,228Filed 25 Sep 2020

Published

31 Mar 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification28 codes

H10D 64/01326
Characterised by the conductor: aspects related to lithography, isolation or planarisation of the conductor
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 30/031
Of FETs having insulated gates [IGFET]: of thin-film transistors [TFT]
H10D 30/501
Field-effect transistors [FET]: fETs having stacked nanowire, nanosheet or nanoribbon channels

Gate spacing in integrated circuit structures

Life of this patent

Gate spacing in integrated circuit structures

Life of this patent

Abstract

Claims20