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US 2022/0101939 A1Published application
Memory device with pipelined access
AssigneesSharp Fukuyama Semiconductor Co., Ltd., Tohoku University
InventorsSHIGEO OHYAMA, TETSUO ENDOH
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Abstract
A memory device includes: a memory cell capable of holding data; and an ECC circuit capable of generating a correction code and detecting an error based on the correction code. The memory cell is accessed by a pipeline operation. The pipeline operation includes at least four pipeline stages including a read cycle reading data from the memory cell, an ECC cycle executing generation of the correction code or error detection for the memory cell in the ECC circuit, a wait cycle during which processing for data related to the memory cell is not executed, and a write cycle writing data into the memory cell.
Claims21
A memory device comprising:
- a memory cell capable of holding data;
- an ECC circuit capable of generating a correction code and detecting an error based on the correction code;
- and
- at least two address buffers,
- wherein the memory cell is accessed by a pipeline operation, and the pipeline operation includes at least four pipeline stages including
- a read cycle reading data from the memory cell,
- an ECC cycle executing generation of the correction code or error detection for the memory cell in the ECC circuit,
- a wait cycle during which processing for data related to the memory cell is not executed and
- a write cycle writing data into the memory cell, and
- wherein the address buffers include
- a write address buffer capable of holding an address of the memory cell received from an outside during an operation of writing data, and
- a read address buffer capable of holding an address of the memory cell received from an outside during an operation of reading data.
9 more elements
(canceled)
A memory device comprising:
- a memory cell capable of holding data;
- and
- an ECC circuit capable of generating a correction code and detecting an error based on the correction code,
- wherein the memory cell is accessed by a pipeline operation, and the pipeline operation includes at least four pipeline stages including
- a read cycle reading data from the memory cell,
- an ECC cycle executing generation of the correction code or error detection for the memory cell in the ECC circuit,
- a wait cycle during which processing for data related to the memory cell is not executed and
- a write cycle writing data into the memory cell,
- the pipeline operation during an operation of reading data from the memory cell is executed in order of the read cycle, the ECC cycle, the wait cycle, and the write cycle, and
- the pipeline operation during an operation of writing data into the memory cell is executed in order of the read cycle, the wait cycle, the ECC cycle, and the write cycle.
7 more elements
A memory device comprising:
- a memory cell capable of holding data;
- and
- an ECC circuit capable of generating a correction code and detecting an error based on the correction code,
- wherein the memory cell is accessed by a pipeline operation, and the pipeline operation includes at least four pipeline stages including
- a read cycle reading data from the memory cell,
- an ECC cycle executing generation of the correction code or error detection for the memory cell in the ECC circuit,
- a wait cycle during which processing of data related to the memory cell is not executed and
- a write cycle writing data into the memory cell,
- wherein, during an operation of writing data into the memory cell, read data read from the memory cell in the read cycle is compared with write data received from an outside, and
- as a result of the comparison, when the read data read is different from the write data, the write data is written into the memory cell.
7 more elements
A memory device comprising:
- a memory cell capable of holding data;
- and
- an ECC circuit capable of generating a correction code and detecting an error based on the correction code,
- wherein the memory cell is accessed by a pipeline operation, and the pipeline operation includes at least four pipeline stages including
- a read cycle reading data from the memory cell,
- an ECC cycle executing generation of the correction code or error detection for the memory cell in the ECC circuit,
- a wait cycle during which processing for data related to the memory cell is not executed and
- a write cycle writing data into the memory cell, and
- the number of pipeline stages in the pipeline operation is different between a data write operation and a data read operation into and from the memory cell.
6 more elements
Dependencies are inferred from the claim text.