Testing magnetoresistive random access memory for low likelihood failure

An apparatus for testing a Magnetoresistive Random Access Memory (MRAM) device, the apparatus comprising:

• a probe array configured to be coupled to the MRAM device to provide a write pulse and a read bias and receive a read signal;
• one or more measurement circuits that provide measurements of the read signal;
• at least one memory;
• and
• at least one processor coupled to the probe array, the one or more measurement circuits, and the at least one memory, the at least one processor being configured to:
• perform a plurality of test cycles on the MRAM device at a first frequency, wherein each test cycle comprises a write operation and a read operation applied to the MRAM device that produces the read signal from the MRAM device;
• perform a first tier of measurement on the MRAM with the one or more measurement circuits to determine whether a switching failure occurs in the MRAM device at each test cycle by comparing the read signal from the MRAM device to a target level;
• perform a second tier of measurement on the MRAM device with the one or more measurement circuits to measure one or more switching performance parameters of the MRAM device while in the MRAM device is in a failure state;
• and
• record the one or more switching performance parameters of the MRAM device for each occurrence of the switching failure.

An apparatus of testing a Magnetoresistive Random Access Memory (MRAM) device, comprising:

• means for performing a plurality of test cycles on the MRAM device at a first frequency, wherein each test cycle comprises a write operation and a read operation applied to the MRAM device that produces a read signal from the MRAM device;
• means for performing a first tier of measurement to determine whether a switching failure occurs in the MRAM device at each test cycle by comparing the read signal from the MRAM device to a target level;
• means for pausing the test cycles after the switching failure occurs and performing a second tier of measurement on the MRAM device before resuming the test cycles at the first frequency, the second tier of measurement comprising measuring one or more switching performance parameters of the MRAM device while in the MRAM device is in a failure state;
• and
• means for recording the one or more switching performance parameters of the MRAM device for each occurrence of the switching failure.