Memory device including massbit counter and method of operating the same

A controller in communication with a plurality of memory cells of a memory apparatus, the controller configured to:

• instruct the memory apparatus to perform a first programming loop including iteratively programming each of the plurality of memory cells to one of a plurality of first program states and verifying that one or more of the plurality of memory cells has a threshold voltage above one of a plurality of first verify voltages corresponding to the plurality of first program states;
• and
• instruct the memory apparatus to perform a second programming loop including iteratively programming each of the plurality of memory cells to one of a plurality of second program states and verifying that at least one of the plurality of memory cells has the threshold voltage above one of a plurality of second verify voltages corresponding to the plurality of second program states.

A method of operating a memory apparatus including a plurality of memory cells, the method comprising:

• performing a first programming loop including programming each of the plurality of memory cells to one of a plurality of first program states and verifying that one or more of the plurality of memory cells has a threshold voltage above one of a plurality of first verify voltages corresponding to the plurality of first program states;
• and
• performing a second programming loop including programming each of the plurality of memory cells to one of a plurality of second program states and verifying that at least one of the plurality of memory cells has the threshold voltage above one of a plurality of second verify voltages corresponding to the plurality of second program states.