Semiconductor memory device and method of operating the same
AssigneeSK hynix Inc.
InventorHee Youl LEE
Life of this patent
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Abstract
A semiconductor memory device, and a method of operating the same, includes a memory cell array and a peripheral circuit. The memory cell array includes memory cells, each storing N bits of data. The peripheral circuit performs a program operation on a physical page including selected memory cells. The peripheral circuit is configured to receive pieces of data of N logical pages and program the pieces of data of the N logical pages to the physical page based on a logic code. The logic code is determined to equalize numbers of sensing operations required to read the pieces of data of the N logical pages. Weak read levels are assigned, using the logic code, to read data of a logical page for which the number of sensing operations is smallest.
Claims19
A semiconductor memory device, comprising:
- a memory cell array including a plurality of memory cells, each of which stores N bits of data, where N is a natural number of 2 or more;
- and
- a peripheral circuit configured to perform a program operation on a physical page including memory cells selected from among the plurality of memory cells,
- wherein the peripheral circuit is configured to receive data corresponding to N logical pages and program the data corresponding to the N logical pages to the physical page based on a logic code,
- wherein the logic code is determined to equalize numbers of sensing operations required to read the data corresponding to the N logical pages, respectively, and
- wherein weak read levels are assigned, according to the logic code, to read data of a logical page, among the N logical pages, for which the number of sensing operations is smallest.
A method of operating a semiconductor memory device including a plurality of memory cells, wherein each of the memory cells stores N bits of data and memory cells included in one physical page store data corresponding to N logical pages, the method comprising:
- receiving data corresponding to N logical pages from a memory controller;
- determining threshold voltage states of memory cells selected from among the plurality of memory cells based on the data corresponding to the N logical pages and a logic code;
- and
- programming the selected memory cells based on the determined threshold voltage states,
- wherein the logic code is determined to equalize numbers of sensing operations required to read the data corresponding to the N logical pages, respectively, and
- wherein weak read levels are assigned, according to the logic code, to read data of a logical page, among the N logical pages, for which the number of sensing operations is smallest.
A semiconductor memory device, comprising:
- a memory cell array including a plurality of memory cells, each of which stores N bits of data, where N is a natural number of 2 or more;
- and
- a peripheral circuit configured to perform a program operation on a physical page including memory cells selected from among the plurality of memory cells,
- wherein the peripheral circuit is configured to receive data corresponding to N logical pages and program the data corresponding to the N logical pages to the physical page based on a logic code,
- wherein the logic code is determined to equalize numbers of sensing operations required to read the data corresponding to the N logical pages, respectively, and
- wherein, among a first read level to a (2N−1)-th read level having sequential magnitudes to distinguish 2N threshold voltage states from each other, the first read level that is a lowest read level and the (2N−1)-th read level that is a highest read level are assigned to read data corresponding to different logical pages among the data corresponding to the N logical pages.
Dependencies are inferred from the claim text.