Non-volatile memory with switchable erase methods
AssigneeSanDisk Technologies LLC
InventorsKen Oowada, Huai-Yuan Tseng
Life of this patent
Estimating the term…
Abstract
To improve the erase process, multiple methods of erasing are utilized. A first method of erasing is relied on at the beginning of life of the memory system. A second method is increasingly relied on as the memory system is used and undergoes many program/erase cycles. In one example, the first method of erase includes applying an erase enable voltage separately to different subsets of the word lines while word lines not receiving the erase enable voltage receive an erase inhibit voltage. In one example, the second method of erase includes applying an erase enable voltage concurrently to all subsets of the word lines.
Claims19
A non-volatile memory system, comprising:
- a group of non-volatile memory cells;
- and
- a control circuit connected to the group of non-volatile memory cells, the control circuit is configured to perform an erase process for the group of non-volatile memory cells by separately in time performing an erase operation on each subset of subsets of the group of non-volatile memory cells and subsequently performing an erase operation concurrently on all non-volatile memory cells of the group of non-volatile memory cells.
A method, comprising:
- performing multiple iterations of an erase process to erase a group of non-volatile memory cells, the group of non-volatile memory cells are connected to a set of word lines, each iteration of the erase process includes applying an erase voltage to the group of non-volatile memory cells as one or more voltage pulses, a first iteration of the erase process includes performing a first method of erase that comprises applying an erase enable voltage separately in time to different subsets of the word lines while word lines not receiving the erase enable voltage receive an erase inhibit voltage;
- and
- switching from performing the first method of erase to performing a second method of erase for one or more additional iterations of the erase process after a metric has exceeded a threshold, the second method of erase includes applying an erase enable voltage concurrently to all the different subsets of the word lines.
-13. (canceled)
A non-volatile memory system, comprising:
- a group of non-volatile memory cells;
- and
- a control circuit connected to the group of non-volatile memory cells, the control circuit is configured to erase the group of non-volatile memory cells by performing iterations of an erase process, during each iteration the control circuit is configured to apply a first selected erase enable voltage to a first set of word lines while applying a first unselected erase voltage to a second set of word lines and subsequently apply a second selected erase enable voltage to the second set of word lines while applying a second unselected erase voltage to the first set of word lines, and the control circuit is configured to change the first unselected erase voltage and the second unselected erase voltage over time while performing the iterations of the erase process such that the first unselected erase voltage approaches the first selected erase enable voltage and the second unselected erase voltage approaches the second selected erase enable voltage.
Dependencies are inferred from the claim text.