Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsMasanobu SHIRAKAWA, Takuya FUTATSUYAMA
Life of this patent
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Abstract
According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.
Claims20
A semiconductor memory device comprising:
- a first memory cell;
- a second memory cell;
- a first word line coupled to the first memory cell;
- a second word line coupled to the second memory cell;
- and
- a first bit line capable of being electrically coupled to both the first memory cell and the second memory cell,
- wherein the first memory cell faces the second memory cell with a semiconductor layer interposed therebetween,
- the device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell, wherein
- in the first operation, a first voltage is applied to the second word line,
- in the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line, and
- in the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.
A semiconductor memory device comprising:
- a first memory cell;
- a second memory cell;
- a first word line coupled to the first memory cell;
- a second word line coupled to the second memory cell;
- and
- a first bit line capable of being electrically coupled to both the first memory cell and the second memory cell,
- wherein the first memory cell faces the second memory cell with a semiconductor layer interposed therebetween,
- wherein the device is configured to execute a first operation, a second operation, and a third operation, wherein
- in the first operation, a first voltage is applied to a word line corresponding to a non-selected memory cell,
- in the second operation, after the first operation, a second voltage higher than the first voltage is applied to the word line corresponding to the non-selected memory cell,
- in the third operation, after the second operation, a third voltage higher than the second voltage is applied to the word line corresponding to the non-selected memory cell, and a fourth voltage lower than both the third voltage and the second voltage is applied to a word line corresponding to a selected memory cell,
- the device is further configured to:
- execute the first operation, the second operation, and the third operations when receiving a write command for the first memory cell, and
- execute the third operation without the first and second operations executed during a period between the device entering to a busy state and returning to a ready state when receiving a write command for the second memory cell.
Dependencies are inferred from the claim text.