US 2022/0101918 A1Published application

Passive compensation for electrical distance

AssigneeMicron Technology, Inc.

InventorsJohn Fredric Schreck, Hari Giduturi

Life of this patent

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Abstract

An architecture of the memory device may leverage a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loads in accessing a memory cell. A memory cell of such a memory device may experience a total resistance including a transmission path resistance associated with the respective access lines of the memory cell and an added compensatory resistance. The foregoing memory device may leverage a spike mitigation scheme to mitigate the harmful effect of a voltage and/or rush current to the near memory cells of the memory device. In addition, spike mitigation circuitry may include coupling a resistor on access lines near the respective decoders. Further, spike mitigation circuitry may include coupling a resistor between the decoders.

Claims20

Dependent claims

An apparatus, comprising:

a memory array comprising a plurality of memory cells disposed between at least two access lines of a plurality of access lines of the memory array, wherein:
a first access line of the plurality of access lines comprises a first electrical current path configured to provide access to a target memory cell of the plurality of memory cells on a first side of the target memory cell, wherein the first electrical current path comprises a first parasitic electrical resistance associated with accessing the target memory cell;
and
a second access line of the plurality of access lines comprises a second electrical current path configured to provide access to the target memory cell on a second side of the target memory cell, wherein a first one or more transistors are coupled to the second access line between at least two memory cells of the plurality of memory cells and configured to provide a first compensatory resistance when providing access to the target memory cell, and wherein the second electrical current path comprises a second parasitic electrical resistance associated with accessing the target memory cell.

1 more element

A semiconductor device, comprising:

a memory array comprising:
a plurality of memory cells;
a first one or more transistors arranged between at least a first two memory cells of the plurality of memory cells;
and
a plurality of access lines, wherein a first access line of the plurality of access lines is configured to provide a first voltage to access a first side of a first memory cell of the at least the first two memory cells of the plurality of memory cells, wherein the first voltage is independent of a location of the first memory cell in the memory array based on the first access line having a first resistance associated with accessing the first memory cell that is independent of the location of the first memory cell in the memory array based on using the first one or more transistors arranged between the at least the first two memory cells of the plurality of memory cells.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/549,390Filed 13 Dec 2021
Priority: 13 May 2020
Published: 31 Mar 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 13/0026
Address circuits or decoders: bit-line or column circuits
G11C 13/0033
Auxiliary circuits: disturbance prevention or evaluation; Refreshing of disturbed memory data
G11C 13/0023
Auxiliary circuits: address circuits or decoders
G11C 13/0028
Address circuits or decoders: word-line or row circuits

Family

Application15/931,080Continuation · filed 13 May 2020
Application17/549,390Continuation
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US 11,749,342 B2Related patent
US 2021/0358545 A1Published application
US 2022/0101918 A1This patent

From the US filing history. Foreign family members aren’t listed.