Memory device
AssigneesSharp Fukuyama Semiconductor Co., Ltd., Tohoku University
InventorsYOSHIHISA SEKIGUCHI, TETSUO ENDOH
Life of this patent
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Abstract
A memory device includes: a cell array that includes a first region including first memory cells and a second region including second memory cells; first word lines connected to each of the first memory cells; second word lines connected to each of the second memory cells; a first bit line commonly connected to the first memory cells and the second memory cells; a row decoder that selects one of the first word lines and one of the second word lines in parallel during a data read operation; and a sense amplifier between the first region and the second region and electrically connected to the first bit line during the data read operation.
Claims22
A memory device comprising:
- a cell array that includes a first region including a plurality of first memory cells and a second region including a plurality of second memory cells;
- a plurality of first word lines connected to each of the plurality of first memory cells;
- a plurality of second word lines connected to each of the plurality of second memory cells;
- a first bit line commonly connected to the plurality of first memory cells and the plurality of second memory cells;
- a row decoder that selects one of the first word lines and one of the second word lines in parallel in accordance with a row address during a data read operation;
- and
- a sense amplifier provided between the first region and the second region and electrically connected to the first bit line during the data read operation.
Dependencies are inferred from the claim text.