Memory Bit Cell for In-Memory Computation
AssigneeApple Inc.
InventorsMichael A. Dreesen, Ajay Bhatia, Michael R. Seningen, Greg M. Hess, Siddhesh Gaiki
Life of this patent
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Abstract
A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.
Claims20
An apparatus, comprising:
- a sign data storage cell configured to:
- store a sign value associated with a weight value;
- and
- couple, based on the sign value, either a compute word line or a complement compute word line to a compute select line.
- a plurality of compute data storage cells, wherein a given compute data storage cell includes a capacitor, and wherein the given compute data storage cell is configured to:
- store a corresponding bit of the weight value;
- and
- couple, based on the corresponding bit and a voltage level of the compute select line, a respective amount of charge onto a compute bit line via the capacitor;
- a control circuit configured to generate, using an operand value, respective voltage levels on the compute word line and the complement compute word line;
- and
- an analog-to-digital converter circuit configured to generate, based on a voltage level of the compute bit line, a plurality of output bits whose value is indicative of a product of the operand value and the weight value.
A method, comprising:
- receiving an operand by a compute-memory circuit that includes a plurality of data storage cells;
- decoding, by the compute-memory circuit, the operand to generate a plurality of select signals;
- setting, using the plurality of select signals, a voltage level of a compute select line;
- coupling, by a subset of the plurality of data storage cells via corresponding ones of a plurality of capacitors, a respective amounts of charge onto a compute bit line using the compute select line, wherein each one of the subset of the plurality of data storage cells is configured to store a respective bit of a plurality of weight bits included in a weight value;
- and
- generating, using a voltage level of the compute bit line, a plurality of output bits whose value is indicative of a product of the operand and the weight value.
An apparatus, comprising:
- a processor circuit;
- a compute-memory circuit coupled to the processor circuit, wherein the compute-memory circuit includes a plurality of data storage cells, and wherein the compute-memory circuit is configured to:
- receive an operand from the processor circuit;
- decode the operand to generate a plurality of select signals;
- set a voltage level of a compute select line using the plurality of select signals;
- couple, via a plurality of capacitors included in a subset of the plurality of data storage cells, respective amounts of charge onto a compute bit line using the compute select line and data stored in the subset of the plurality of data storage cells, wherein the data is indicative of a weight value;
- and
- generate an output value using the voltage level of the compute bit line, wherein the output value is indicative of a product of the operand and the weight value.
Dependencies are inferred from the claim text.