Variable width memory module supporting enhanced error detection and correction

A memory module comprising:

• a primary data link, a first secondary data link, and a second secondary data link;
• a first memory component coupled to the first secondary data link;
• and
• a second memory component coupled to the second secondary data link;
• the memory module operable in:
• a first mode in which the memory module, responsive to successive first and second read commands to the first memory component and the second memory component, respectively, successively conveys over the primary data link first read data from the first memory component via the first secondary data link and second read data from the second memory component via the second secondary data link;
• and
• a second mode in which the memory module, responsive to the successive first and second read commands to the first memory component and the second memory component, respectively, interleaves over the primary data link the first read data from the first memory component via the first secondary data link and the second read data from the second memory component via the second secondary data link.

A memory module comprising:

• a module command link to receive module commands;
• and
• memory slices coupled to the primary data link, each memory slice including:
• first, second, third, and fourth memory components;
• first, second, third, and fourth memory-component links of a memory-component width and respectively coupled to the first, second, third, and fourth memory components;
• first and second primary data links, each of the memory-component width, to communicate module data responsive to the module commands;
• and
• multiplexing logic to convey data from successive pairs of the first, second, third, and fourth memory components responsive to one of the module commands.

A method comprising:

• receiving a primary read command;
• deriving, from the primary read command, secondary read commands and at least one buffer command;
• sending a first of the secondary read commands to a first memory component and a second of the secondary read commands to a second memory component, the first memory component issuing first read data responsive to the first secondary read command and the second memory component issuing second read data responsive to the second secondary read command;
• and
• sending the at least one buffer command to a data-buffer component coupled to the first memory component and the second memory component, the data-buffer component interleaving the first read data with the second read data responsive to the at least one buffer command.