US 2022/0101909 A1 · MULTI-DECK NON-VOLATILE MEMORY ARCHITECTURE WITH IMPROVED WORDLINE BUS AND BITLINE BUS CONFIGURATION

Abstract

Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction.

Claims20

Dependent claims

A semiconductor apparatus comprising:

one or more substrates;
and
a plurality of decks of a multi-deck non-volatile memory coupled to the one or more substrates, at least one of the plurality of decks comprising:
a partition including a plurality of memory tile rows, a plurality of memory tile columns, and a memory tile, wherein the memory tile includes a data circuit coupled to a plurality of memory cells, wherein the data circuit is to access a data state of a plurality of memory cells,
a first termination tile located at one end of one of the plurality of memory tile rows, and
a first wordline bus coupled to the data circuit, wherein the first wordline bus is located over the first termination tile and at least a portion of the memory tile.

3 more elements

A system comprising:

a memory controller;
and
a multi-deck non-volatile memory structure coupled to the memory controller, the multi-deck non-volatile memory structure comprising a plurality of decks, at least one of the plurality of decks comprising:
a partition comprising a plurality of memory tile rows, a plurality of memory tile columns, and a memory tile, wherein the memory tile includes a data circuit coupled to a plurality of memory cells, and wherein the data circuit is to access a data state of a plurality of memory cells,
a first termination tile located at one end of one of the plurality of memory tile rows, and
a first wordline bus coupled to the data circuit, wherein the first wordline bus is located over the first termination tile and at least a portion of the memory tile.

3 more elements

Dependencies are inferred from the claim text.

Multi-deck non-volatile memory architecture with improved wordline bus and bitline bus configuration

Life of this patent

Multi-deck non-volatile memory architecture with improved wordline bus and bitline bus configuration

Life of this patent

Abstract

Claims20