Memory controller with clock-to-strobe skew compensation
AssigneeRambus Inc.
InventorFrederick A. Ware
Life of this patent
Estimating the term…
Abstract
An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.
Claims21
1-21. (canceled)
An integrated circuit device comprising:
- a clock signal driver to output a clock signal to a dynamic random access memory device (DRAM) via a clock signal line;
- and
- a data timing signal driver to output to the DRAM via a data timing signal line:
- a sequence of calibration data timing signals having respective phase offsets relative to the clock signal to enable, during a timing calibration operation, identification of a phase offset of one of the calibration data timing signals that compensates for a difference in signal propagation times over the clock signal line and data timing signal line;
- and
- during a memory write operation, a write data timing signal having the identified phase offset.
A method of operation within an integrated circuit device, the method comprising:
- outputting a clock signal to a dynamic random access memory device (DRAM) via a clock signal line;
- and
- outputting to the DRAM, via a data timing signal line and during a timing calibration operation, a sequence of calibration data timing signals having respective phase offsets relative to the clock signal to enable identification of a phase offset of one of the calibration data timing signals that compensates for a difference in signal propagation times over the clock signal line and data timing signal line;
- and
- outputting to the DRAM, via the data timing signal line and during a memory write operation, a write data timing signal having the identified phase offset.
An integrated circuit device comprising:
- means for outputting a clock signal to a dynamic random access memory device (DRAM) via a clock signal line;
- and
- means for outputting to the DRAM, via a data timing signal line and during a timing calibration operation, a sequence of calibration data timing signals having respective phase offsets relative to the clock signal to enable identification of a phase offset of one of the calibration data timing signals that compensates for a difference in signal propagation times over the clock signal line and data timing signal line;
- and
- means for outputting to the DRAM, via the data timing signal line and during a memory write operation, a write data timing signal having the identified phase offset.
Dependencies are inferred from the claim text.