Non-volatile memory with virtual ground voltage provided to unselected column lines during memory write operation

A non-volatile memory comprising:

• virtual ground circuitry coupled to a first power supply terminal and a second power supply terminal and configured to generate a virtual ground voltage at a virtual ground node, wherein the first power supply terminal is configured to provide a first power supply voltage and the second power supply terminal is configured to provide a second power supply voltage which is less than the first power supply voltage, wherein the virtual ground voltage is greater than zero volts and is between the first power supply voltage and the second power supply voltage;
• a memory array of memory cells, each memory cell of the memory array including a select transistor and a storage element for storing a value, wherein each memory cell is coupled to a first column line of a plurality of first column lines;
• a first decoder configured to select a set of first column lines from the plurality of first column lines for a memory write operation to a selected set of the memory cells coupled to the selected set of first column lines;
• write circuitry configured to receive a write value for storage into the selected set of memory cells during the memory write operation;
• and
• a first column line multiplexer (MUX) configured to couple each selected first column line of the set of first column lines to the write circuitry during the memory write operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory write operation,
• wherein the virtual ground circuitry comprises:
• a current compensator coupled to the virtual ground node via a first enable switch, wherein the first enable switch is configured to be conductive to couple the current compensator to the virtual ground node during a memory read operation.

A non-volatile memory comprising:

• virtual ground circuitry coupled to a first power supply terminal and a second power supply terminal and configured to generate a virtual ground voltage at a virtual ground node, wherein the first power supply terminal is configured to provide a first power supply voltage and the second power supply terminal is configured to provide a second power supply voltage which is less than the first power supply voltage, wherein the virtual ground voltage is at least 100 mV greater than the second power supply voltage and less than the first power supply voltage;
• a memory array of memory cells, each memory cell of the memory array including a select transistor and a storage element for storing a value, wherein each memory cell is coupled to a source line of a plurality of source lines and to a bit line of a plurality of bit lines;
• a decoder configured to select a set of source lines from the plurality of source lines and a set of bit lines from the plurality of bit lines for a memory write operation to a selected set of the memory cells coupled to the selected set of source lines and the selected set of bit lines;
• write circuitry configured to receive a write value for storage into the selected set of memory cells during the memory write operation;
• a source line multiplexer (MUX) configured to couple each selected source line of the set of source lines to the write circuitry during the memory write operation, and configured to couple each unselected source line of the plurality of source lines to the virtual ground node during the memory write operation;
• and
• a bit line MUX configured to couple each selected bit line of the set of bit lines to the write circuitry during the memory operation, and configured to couple each unselected bit line of the plurality of bit lines to the virtual ground node during the memory write operation,
• wherein the virtual ground circuitry comprises:
• a flipped voltage follower circuit having a current source coupled in series with a source follower transistor and a sink transistor between the first power supply terminal and the second power supply terminal, wherein a first current electrode of the source follower transistor is coupled to the current source, and a second current electrode of the source follower transistor is coupled to the virtual ground node.

In a memory having a first power supply terminal configured to provide a first supply voltage, a second power supply terminal configured to provide a second supply voltage less than the first supply voltage, and a memory array of memory cells in which each memory cell is coupled to a first column line of a plurality of first column lines, a method comprising:

• selecting a set of first column lines from the plurality of first column lines for a memory write operation of a write value to a selected set of the memory cells coupled to the selected set of first column lines;
• generating a virtual ground voltage at a virtual ground node, wherein the virtual ground voltage is greater than the second supply voltage, and less than the first power supply voltage, wherein in a flipped voltage follower circuit having a current source coupled in series with a source follower transistor and a sink transistor between the first power supply terminal and the second power supply terminal, a first current electrode of the source follower transistor is coupled to the current source, and a second current electrode of the source follower transistor is coupled to the virtual ground node to generate the virtual ground voltage;
• and
• during the memory write operation:
• coupling all unselected first column lines of the plurality of first column lines to the virtual ground node;
• coupling each first column line of the selected set of first column lines to write circuitry configured to receive the write value, in which each memory cell of the selected set of memory cells stores a corresponding unique bit of the write value;
• and
• providing a current through each memory cell of the selected set of memory cells based on the write value, wherein, for each memory cell, the current is provided through the memory cell in a first direction when the corresponding unique bit has first value, and in a second direction, opposite the first direction, when the corresponding unique bit has a second value, different from the first value.