Programmable logic circuit, information processing apparatus, and non-transitory computer readable medium
AssigneeFUJIFILM Business Innovation Corp.
InventorHiroaki SHIOKAWA
Life of this patent
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Abstract
A programmable logic circuit includes multiple logic blocks that are connected communicatively, wherein multiple modules are reconfigured in any of the logic blocks, and wherein the modules include a first module that is being executed and a second module that is not being executed, and start of execution of the second module is delayed from a start time point of execution of the first module so as to obtain a state in which a first time at which the first module accesses a memory does not overlap a second time at which the second module accesses the memory.
Claims20
A programmable logic circuit comprising:
- a plurality of logic blocks that are connected communicatively,
- wherein a plurality of modules are reconfigured in any of the plurality of logic blocks, and
- wherein the plurality of modules include a first module that is being executed and a second module that is not being executed, and start of execution of the second module is delayed from a start time point of execution of the first module so as to obtain a state in which a first time at which the first module accesses a memory does not overlap a second time at which the second module accesses the memory.
An information processing apparatus comprising:
- a processor that is connected to a programmable logic circuit,
- wherein the processor is configured to:
- reconfigure a plurality of modules in the programmable logic circuit;
- predict a first time at which a first module accesses a memory, the first module being executed and being among the plurality of modules;
- predict a second time at which a second module accesses the memory, the second module being not executed and being among the plurality of modules;
- and
- delay start of execution of the second module from a start time point of execution of the first module so as to obtain a state in which the second time does not overlap the first time.
A non-transitory computer readable medium storing a program causing a computer to execute a process, the computer having a processor connected to a programmable logic circuit, the process comprising:
- reconfiguring a plurality of modules in the programmable logic circuit;
- predicting a first time at which a first module accesses a memory, the first module being executed and being among the plurality of modules;
- and
- predicting a second time at which a second module accesses the memory, the second module being not executed and being among the plurality of modules, and delaying start of execution of the second module from a start time point of execution of the first module so as to obtain a state in which the second time does not overlap the first time.
Dependencies are inferred from the claim text.