US 2022/0101896 A1 · DATA STRUCTURES WITH MULTIPLE READ PORTS

Abstract

A memory structure having 2m read ports allowing for concurrent access to n data entries can be constructed using three memory structures each having 2′ read ports. The three memory structures include two structures providing access to half of the n data entries, and a difference structure providing access to difference data between the halves of the n data entries. Each pair of the 2m ports is connected to a respective port of each of the 2m-1-port data structures, such that each port of the part can access data entries of a first half of the n data entries either by accessing the structure storing that half directly, or by accessing both the difference structure and the structure containing the second half to reconstruct the data entries of the first half, thus allowing for a pair of ports to concurrently access any of the stored data entries in parallel.

Claims11

Dependent claims

(canceled)

A memory configured to allow for concurrent read requests for data from each of a plurality of output read ports, comprising:

first, second, and third memory sub-structures each storing at least respective subsets of data, each memory sub-structure having respective first and second read ports through which any data of the subset of data stored by the sub-structure can be read concurrently in parallel, and wherein the respective subsets of data comprise a first subset, second subset, and difference subset generated from the first and second subsets, respectively;
a first access circuit connected to the first read ports of each of the first, second, and third memory sub-structures, and
a second access circuit connected to the second read ports of each of the first, second, and third memory sub-structures,
wherein each of the first and second access circuits comprise respective first and second output read ports, and are configured to satisfy concurrent read requests for data of the first subset from both the first and second output read ports by passing data from the first memory sub-structure to the first output read port and concurrently passing data reconstructed using data from the second and third memory sub-structures to the second output read port.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

17/397,158Filed 9 Aug 2021

Priority

15 Sep 2017

Published

31 Mar 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 7/1075
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: for multiport memories each having random access…
G06F 9/3001
To perform operations on data operands: arithmetic instructions
G06F 9/30029
To perform operations on data operands: logical and Boolean instructions, e.g. XOR, NOT
G06F 9/3004
Arrangements for executing specific machine instructions: to perform operations on memory

Family

Application62/559,390Us provisional application · filed 15 Sep 2017

Application16/132,196Continuation · filed 14 Sep 2018

Application17/397,158Continuation

US 11,114,138 B2Related patent

US 11,875,874 B2Related patent

US 2019/0206454 A1Published application

US 2022/0101896 A1This patent

From the US filing history. Foreign family members aren’t listed.

Data structures with multiple read ports

Life of this patent

Data structures with multiple read ports

Life of this patent

Abstract

Claims11