Memory device supporting dbi interface and operating method of memory device

A memory device comprising:

• a plurality of memory chips configured to receive a packet including a header and a data region from a controller,
• wherein each of the memory chips comprises:
• a plurality of input/output pads configured to respectively receive a plurality of data signals from the controller;
• a data bus inversion (DBI) pad configured to receive a DBI signal from the controller;
• and
• an interface circuit configured to count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the plurality of data signals and the DBI signal and determine the plurality of data signals as the header or the data region based on the first number and the second number.

A memory device configured to receive a packet including a header and a data region from a controller, the memory device comprising:

• a memory cell array including a plurality of memory cells;
• a page buffer connected to the memory cell array;
• a control logic circuit configured to control an operation of the memory cell array;
• a plurality of input/output pins configured to respectively receive a plurality of data signals from the controller;
• a data bus inversion (DBI) pin configured to receive a DBI signal from the controller;
• and
• an interface circuit configured to count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the plurality of data signals and the DBI signal, determine the plurality of data signals as the header or the data region based on the first number and the second number, determine the data region as data, a command, or an address based on bits included in the header, provide the data to the page buffer, and provide the command or the address to the control logic circuit.