US 2022/0101894 A1 · MEMORY DEVICE INCLUDING MULTIPLE MEMORY CHIPS AND DATA SIGNAL LINES AND A METHOD OF OPERATING THE MEMORY DEVICE

Abstract

An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.

Claims20

Dependent claims

An operating method of a memory device, the method comprising:

in response to a selection control signal, selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver, wherein the plurality of memory chips share a plurality of data signal lines, wherein each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip;
in response to mode register setting command signals, setting each ODT resistor which is connected to a first receiver to a first resistance value, and setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value;
and
setting an amplification strength of an equalizer circuit of each first receiver by performing training operations,
wherein each data signal line of the plurality of data signal lines is respectively connected to a first receiver.

2 more elements

A memory device comprising a plurality of memory chips which share a plurality of data signal lines,

wherein each of the plurality of memory chips comprises:
a plurality of input/output pads which are respectively connected to the plurality of data signal lines;
and
a plurality of on-die termination (ODT) resistors which are respectively connected to the input/output pads, and
wherein each of the plurality of memory chips is configured to:
select a first pad from among the plurality of input/output pads in response to a selection control signal;
set an ODT resistor which is connected to the first pad to a first resistance value in response to a mode register setting command signal;
and
set each ODT resistor which is connected to a non-selected input/output pad of the plurality of input/output pads to a second resistance value,
wherein each data signal line is respectively connected to a first pad.

7 more elements

Dependencies are inferred from the claim text.

Memory device including multiple memory chips and data signal lines and a method of operating the memory device

Life of this patent

Memory device including multiple memory chips and data signal lines and a method of operating the memory device

Life of this patent

Abstract

Claims20