Semiconductor memory device, processing system including the same and power control circuit for the same
AssigneeSK hynix Inc.
InventorChang Hyun KIM
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device may include a plurality of memory cells wherein identifiers may be provided to the memory cells, The semiconductor memory device may include a first circuit, a second circuit and a power control circuit. The first circuit may include a first power terminal and a second power terminal. The second circuit may include a third terminal and a fourth terminal, The power control circuit may be configured to apply a first power voltage or a ground voltage to the first power terminal and to apply the ground voltage to the second power terminal based on the identifiers.
Claims18
A semiconductor memory device including a plurality of memory cells to which identifiers are assigned, respectively, the semiconductor memory device comprising:
- a first circuit including a first power terminal and a second power terminal;
- a second circuit including a third power terminal and a fourth power terminal;
- and
- a power control circuit configured to apply a first power voltage or a ground voltage to the first power terminal and the ground voltage to the second power terminal based on the identifiers.
A processing system comprising:
- a base die;
- and
- at least one core the stacked on the base the and coupled to the base die through a connection via, the core die including a plurality of memory cells to which identifiers are assigned, respectively,
- wherein the core die comprises:
- a first circuit including a first power terminal and a second power terminal;
- a second circuit including a third power terminal and a fourth power terminal;
- and
- a power control circuit configured to apply a first power voltage or a ground voltage to the first power terminal and the ground voltage to the second power terminal based on the identifiers.
A processing system comprising
- a base die;
- and
- a stacked structure stacked on the base die and coupled to the base die through a connection via, the stacked structure including a plurality of memory cells to which identifiers are assigned, respectively,
- wherein the stacked structure comprises:
- a master core die directly stacked on the base the, the master core the including a first circuit and a second circuit, a first power terminal of the first circuit configured to receive a first power voltage, a second power terminal of the first circuit configured to receive a ground voltage, a third power terminal of the second circuit configured to receive a second power voltage and a fourth power terminal of the second circuit configured to receive a ground voltage;
- and
- at least one slave core die stacked on or over the master core die, the slave core die including a first circuit and a second circuit, a first power terminal of the first circuit configured to receive a ground voltage, a second power terminal of the first circuit configured to receive a first power voltage, a third power terminal of the second circuit configured to receive a second power voltage and a fourth power terminal of the second circuit configured to receive a ground voltage.
A power control circuit for a plurality of memory dies, the memory dies configured to form a stacked chip package, wherein identifiers are assigned to the memory dies, and each of the memory dies includes a first circuit and a second circuit, the power control circuit comprising:
- a die determination circuit configured to determine stack positions of the memory dies based on the identifiers of the memory dies to output a die attribute signal;
- and
- a current regulation circuit configured to apply a first power voltage or a ground voltage to a first power terminal of the first circuit and apply the ground voltage to a second power terminal of the first circuit based on the die attribute signal.
A power control circuit for a plurality of memory dies, the memory dies configured to form a stacked chip package, wherein identifiers are assigned to the memory dies, and each of the memory dies includes a first circuit and a second circuit, the first circuit having a first power terminal and a second power terminal, the power control circuit comprising:
- a die determination circuit configured to determine stack positions of the memory dies based on the identifiers of the memory dies to output a die attribute signal;
- and
- a current regulation circuit comprising a switch configured to connect the first power terminal with the second power terminal or disconnect the first power terminal from the second power terminal in response to the die attribute signal, wherein a ground voltage may be applied to the first power terminal and the second power terminal to cut off current consumption of the first circuit in response to the die attribute signal.
Dependencies are inferred from the claim text.