Memory interconnection architecture systems and methods

A processing in memory (PIM) chip fabrication process comprising:

• forming a memory array in a memory array area of the PIM chip;
• forming logic components in a logic area of the PIM chip, wherein the logic components include processing components, wherein a portion of the logic components are included in a layer with a portion of the memory array;
• and
• forming an interconnection network including interconnect wires and switches configured to route information, wherein a portion of the interconnect wires are located in a metal layer area that is located above the memory array area, wherein the memory array area includes a memory cell portion and a memory array periphery component portion and the switches are located in the memory array periphery component portion of the memory array area.

A processing in memory (PIM) chip comprising:

• a memory block configured to store information;
• logic components configured to process information stored in the memory block, wherein a portion of the logic components are included in a layer with a portion of the memory block;
• and
• an interconnection network configured to communicatively couple the logic components, wherein the communication network includes interconnect wires, and a portion of the interconnect wires are located in a metal area that is located over the memory block, wherein the interconnection network includes switches in the memory block area and the switches are configured to route information in the interconnection network.