Shift register, gate driving circuit, display device and gate driving method

A shift register, comprising:

• a display pre-charging reset circuit, a sensing control circuit, a sensing pre-charging reset circuit, a pull-down control circuit, a display noise reduction circuit and an output circuit, wherein the sensing control circuit and the sensing pre-charging reset circuit are coupled to a sensing control node;
• the display pre-charging reset circuit, the sensing pre-charging reset circuit, the pull-down control circuit and the output circuit are coupled to a pull-up node, the pull-down control circuit, the display noise reduction circuit and the output circuit are coupled to the pull-down node, and the output circuit is configured with at least one signal output terminal, the output circuit comprises at least one output sub-circuit arranged in one-to-one correspondence to the at least one signal output terminal;
• the display pre-charging reset circuit is coupled to a first signal input terminal, a second signal input terminal, a first scanning power supply terminal and a second scanning power supply terminal, and is configured to write a first scanning voltage provided by the first scanning power supply terminal into the pull-up node in response to a control of the first signal input terminal;
• and write a second scanning voltage provided by said second scanning power supply terminal into the pull-up node in response to a control of the second signal input terminal;
• the sensing control circuit is coupled to the signal output terminal and a random signal terminal, and is configured to write an output signal provided by the signal output terminal into the sensing control node in response to a control of the random signal terminal;
• the sensing pre-charging reset circuit is coupled to a first clock signal terminal, a sensing reset signal terminal and a second power supply terminal, and is configured to write a voltage signal in an active level state into the pull-up node in response to a control of a voltage at the sensing control node;
• and write a second operating voltage provided by the second power supply terminal into the pull-up node in response to a control of the sensing reset signal terminal;
• the pull-down control circuit is coupled to a first power supply terminal and the second power supply terminal, and is configured to write a voltage, with a phase opposite to that of a voltage at the pull-up node, into the pull-down node;
• the display noise reduction circuit is coupled to the first signal input terminal, the second signal input terminal, the first scanning power supply terminal and the second scanning power supply terminal, and is configured to write the second scanning voltage into the pull-down node in response to the control of the first signal input terminal;
• and write the first scanning voltage into the pull-down node in response to the control of the second signal input terminal;
• the output sub-circuit is coupled to the pull-up node, the pull-down node, the corresponding signal output terminal, a corresponding output clock signal terminal and a reset power supply terminal, and is configured to write an output clock signal provided by the corresponding output clock signal terminal into the corresponding signal output terminal in response to a control of the voltage at the pull-up node;
• and write a reset operating voltage provided by the reset power supply terminal into the corresponding signal output terminal in response to a control of a voltage at the pull-down node.