Display device with internal compensation

A display device comprising:

• pixels connected to a first scan line, a second scan line, a third scan line, a data line, a first emission control line, and a second on control line,
• wherein each of the pixels comprises:
• a light emitting element;
• a first transistor connected between a first node coupled to a first power source and a second node coupled to an anode of the light emitting element, and including a gate electrode connected to a third node;
• a second transistor connected between the data line and a fourth node, and including a gate electrode connected to the first scan line;
• a third transistor connected between the third node and a third power source, and including a gate electrode connected to the second scan line;
• a fourth transistor connected between the third node and a fifth node;
• including a date electrode connected to the second scan line;
• a fifth transistor connected between the second node and a fourth power source, and including a note electrode connected to the third scan line;
• and
• a sixth transistor connected between the third node and the fourth node, and include a electrode connected to the first emission control line,
• wherein the third transistor and the fourth transistor are maintained in a turned-on state during an initialization period in which the second node is initialzed by the fourth power source and the fifth node is initialized by the third lower source, a compensation period in which a threshold voltage of the first transistor is compensated, and a data writing period in which a data voltage applied through the data is supplied to the third node, and
• wherein the fifth transistor is turned on during the initialization period.

A pixel unit comprising a plurality of pixels, each pixel comprising:

• a light emitting element including a cathode connected to a second power source;
• a first transistor including a first electrode, a second electrode connected to an anode of the light emitting element, and a gate electrode;
• a third transistor including a first electrode connected to a third power source, a second electrode connected to the gate electrode of the first transistor, and a gate electrode connected to a second scan line;
• a fourth transistor including a first electrode connected to the gate electrode of the first transistor, a second electrode, and a gate electrode connected to the second scan line;
• a first capacitor connected between the second electrode of the first transistor and the second electrode of the fourth transistor;
• and
• a seventh transistor including a first electrode connected to a first power source, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a second emission control line;
• wherein the gate electrode of the first transistor connects the second electrode of the third transistor and the first electrode of the fourth transistor.