Scan driver

A scan driver comprising:

• a plurality of stages,
• wherein a first stage of the plurality of stages includes:
• a first transistor including a gate electrode connected to a first clock terminal, a first electrode connected to a first carry terminal, and a second electrode connected to a first node;
• a second transistor including a gate electrode connected to a second clock terminal, a first electrode connected to the first node, and a second electrode connected to a second power terminal;
• a third transistor including a gate electrode connected to the first node, a first electrode connected to the first clock terminal, and a second electrode connected to a second node;
• a fourth transistor including a gate electrode connected to the first clock terminal, a first electrode connected to a first power terminal, and a second electrode connected to the second node;
• and
• an output portion configured to output a first scan signal to a first output terminal and a second scan signal to a second output terminal, based on a voltage of the first node and a voltage of the second node.

A scan driver comprising:

• a plurality of stages,
• wherein a first stage of the plurality of stages includes:
• a first transistor including a gate electrode connected to a first clock terminal, a first electrode connected to a first carry terminal, and a second electrode connected to a first node;
• a second transistor including a gate electrode connected to a second clock terminal, a first electrode connected to a first power terminal, and a second electrode connected to a second node;
• a third transistor including a gate electrode connected to the first node, a first electrode connected to the first clock terminal, and a second electrode connected to the second node;
• a fourth transistor including a gate electrode connected to the first clock terminal, a first electrode connected to the first power terminal, and a second electrode connected to the second node;
• and
• an output portion configured to output a first scan signal to a first output terminal and a second scan signal to a second output terminal, based on a voltage of the first node and a voltage of the second node.

A stage for a scan driver comprising:

• a first transistor and a fifth transistor that are turned on by a first clock signal, wherein the first transistor is connected to a first node and the fifth transistor is connected to second node;
• a second transistor and a fourth transistor that are turned on by a second clock signal, wherein the second transistor is connected to the first node and the fourth transistor is connected to the second node;
• a third transistor connected to the first node and the second node;
• and
• an output circuit configured to output a first scan signal to a first output terminal and a second scan signal to a second output terminal, based on a voltage of the first node and a voltage of the second node.