Direct-connected machine learning accelerator
AssigneeAdvanced Micro Devices, Inc.
InventorMaxim V. Kazakov
Life of this patent
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Abstract
Techniques are disclosed for communicating between a machine learning accelerator and one or more processing cores. The techniques include obtaining data at the machine learning accelerator via an input/output die; processing the data at the machine learning accelerator to generate machine learning processing results; and exporting the machine learning processing results via the input/output die, wherein the input/output die is coupled to one or more processor chiplets via one or more processor ports, and wherein the input/output die is coupled to the machine learning accelerator via an accelerator port.
Claims20
A processor, comprising:
- one or more processor chiplets;
- an input/output die;
- and
- a machine learning accelerator,
- wherein the one or more processor chiplets are coupled to the input/output die via one or more processor ports of the input/output die;
- and
- wherein the machine learning accelerator is coupled to the input/output die via a machine learning accelerator port of the input/output die.
A method for communicating between a machine learning accelerator and one or more processing cores, the method comprising:
- obtaining data at the machine learning accelerator via an input/output die;
- processing the data at the machine learning accelerator to generate machine learning processing results;
- and
- exporting the machine learning processing results via the input/output die,
- wherein the input/output die is coupled to one or more processor chiplets via one or more processor ports, and
- wherein the input/output die is coupled to the machine learning accelerator via an accelerator port.
A computing device, comprising:
- a processor;
- and
- a memory,
- wherein the processor includes:
- one or more processor chiplets;
- an input/output die;
- and
- a machine learning accelerator,
- wherein the one or more processor chiplets are coupled to the input/output die via one or more processor ports of the input/output die;
- and
- wherein the machine learning accelerator is coupled to the input/output die via a machine learning accelerator port of the input/output die.
Dependencies are inferred from the claim text.