Memory-mapped neural network accelerator for deployable inference systems

A method comprising:

• receiving a neural network description at a neural network processor system via an interface from a host,
• the neural network processor system comprising at least one neural network processing core, an activation memory, an instruction memory, and at least one control register, the neural network processing core adapted to implement neural network computation, control and communication primitives,
• the interface operatively connected to the neural network processor system;
• exposing a memory map via the interface, the memory map comprising regions corresponding to each of the activation memory, instruction memory, and at least one control register;
• receiving input data at the neural network processor system via the interface;
• computing output data from the input data based on the neural network model;
• providing the output data from the neural network processor system via the interface.