Reconfigurable hardware buffer in a neural networks accelerator framework

A system to implement a neural network (NN), the system comprising:

• a host processor;
• a main memory;
• and
• an accelerator framework (AF), the accelerator framework including:
• a plurality of processing circuits including one or more accelerators;
• a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, the reconfigurable hardware buffer having:
• a memory;
• and
• control circuitry;
• and
• a stream switch coupled to the plurality of processing circuits and to the reconfigurable hardware buffer, wherein, in operation,
• a number of the variable number of input data channels is associated with an execution epoch of the NN;
• the stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch;
• and
• the control circuitry of the reconfigurable hardware buffer configures the memory of the reconfigurable hardware buffer to store data of the variable number of input data channels during processing of the execution epoch, the configuring including allocating a portion of the memory of the reconfigurable hardware buffer to each of the variable number of input data channels.

A method, comprising:

• processing an execution epoch of a convolutional neural network using a convolutional accelerator framework having a plurality of processing circuits, a stream switch and a reconfigurable hardware buffer, the processing of the execution epoch including:
• configuring a variable number of input data channels of the reconfigurable hardware buffer of the convolutional accelerator framework, a number of the variable number of input data channels being associated with the execution epoch, the configuring including allocating portions of a memory of the reconfigurable hardware buffer to each of the variable number of input data channels;
• streaming, via the stream switch, data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer;
• and
• storing data of the variable number of input data channels in the memory of the reconfigurable hardware buffer based on the allocating of portions of the memory to the variable number of input data channels.

A non-transitory computer-readable medium having contents that cause one or more hardware processors of a convolutional accelerator framework to perform a method, the method comprising:

• processing an execution epoch of a convolutional neural network, the processing of the execution epoch including:
• configuring a variable number of input data channels of a reconfigurable hardware buffer of the convolutional accelerator framework, a number of the variable number of input data channels being associated with the execution epoch, the configuring including allocating a portion of a memory of the reconfigurable hardware buffer to each of the variable number of input data channels;
• streaming, via a stream switch of the convolutional accelerator framework, data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer;
• and
• storing data of the variable number of input data channels in the memory of the reconfigurable hardware buffer based on the allocating of portions of the memory to the variable number of input data channels.