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US 2022/0100672 A1Published application
Scalable region-based directory
AssigneeAdvanced Micro Devices, Inc.
InventorsAmit Apte, Ganesh Balakrishnan
Life of this patent
Estimating the term…
Abstract
Disclosed is a cache directory including one or more cache directories configurable to interchange within each cache directory entry at least one bit between a first field and a second field to change the size of the region of memory represented and the number of cache lines tracked in the cache subsystem.
Claims21
A method comprising:
- maintaining a cache directory including one or more cache directory entries for tracking cache lines for a first region size;
- and
- configuring the one or more cache directory entries for tracking cache lines for a second region size.
A system comprising:
- one or more home nodes coupled to one or more cache directories, each cache directory configured to change from tracking cache lines for a first region size per cache line entry to tracking cache lines for a second region size per cache line entry, wherein the first region size is associated with a first page size of a memory and the second region size is associated with a second page size of the memory.
A computing device, comprising:
- a cache directory including one or more cache entries and configured to change from tracking cache lines for a first region size per cache line entry to tracking cache lines for a second region size per cache line entry, wherein the first region size is associated with a first page size of a memory and the second region size is associated with a second page size of the memory.
Dependencies are inferred from the claim text.