Memory device
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
InventorsJenn-Gwo HWU, Bo-Jyun CHEN, Kuan-Wun LIN
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Abstract
A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.
Claims20
A memory device, comprising:
- a memory cell comprising:
- a semiconductor substrate;
- a tunneling layer over the semiconductor substrate;
- a storage layer on the tunneling layer;
- a first electrode on the storage layer;
- a second electrode on the tunneling layer, wherein the storage layer has a sidewall facing the second electrode;
- and
- a third electrode spaced apart from the second electrode;
- a writing transistor electrically connected to the first electrode of the memory cell;
- and
- a reading transistor electrically connected to the second electrode of the memory cell.
A memory device, comprising:
- a memory cell comprising:
- a nanowire protruding from a substrate;
- a top tunneling layer above the nanowire;
- a sidewall tunneling layer on a sidewall of the nanowire;
- a storage layer wrapping around the sidewall tunneling layer;
- a first electrode wrapping around the storage layer;
- and
- a second electrode on the nanowire and spaced apart from the storage layer;
- a writing transistor electrically connected to the first electrode of the memory cell;
- and
- a reading transistor electrically connected to the second electrode of the memory cell.
A memory device, comprising:
- a memory cell comprising:
- a first nanowire protruding from a substrate;
- a top tunneling layer above the first nanowire;
- a first electrode wrapping around the first nanowire;
- a storage layer between the first electrode and the first nanowire;
- and
- a second electrode on the top tunneling layer;
- a writing transistor electrically connected to the first electrode of the memory cell and comprising:
- a second nanowire protruding from a substrate;
- a gate electrode wrapping around the second nanowire;
- a gate dielectric layer between the gate electrode and the second nanowire;
- a source/drain portion on the second nanowire, wherein a top surface of the second electrode of the memory cell is higher than a top surface of the source/drain portion of the writing transistor;
- and
- a reading transistor electrically connected to the second electrode of the memory cell.
Dependencies are inferred from the claim text.