A method for manufacturing a fin field-effect transistor, comprising steps of:
- S1:
- forming a plurality of fins on a semiconductor substrate,
- forming a shallow trench between every adjacent two of the plurality of fins and filling the shallow trench with a first field oxide, wherein a top surface of the first field oxide is configured to be lower than a top surface of each of the plurality of fins, wherein the top surface of each of the plurality of fins is exposed above the first field oxide, wherein the plurality of fins is isolated from each other at a lower part by the first field oxide;
- S2:
- forming a polysilicon layer and forming a plurality of polysilicon gates by a photolithography process and an etching process, wherein the plurality of polysilicon gates intersects with the plurality of fins like a grid, and wherein an overlap region of each of the plurality of polysilicon gates and each of the plurality of fins forms a dummy gate structure;
- S3:
- forming a source region and a drain region on each of the plurality of fins, wherein the source region is located on one side of each of the plurality of polysilicon gates and the drain region is located on the other side of each of the plurality of polysilicon gates;
- S4:
- removing the plurality of polysilicon gates, forming a gate dielectric layer, wherein the gate dielectric layer covers the top surface of each of the plurality of fins and the top surface of the first field oxide;
- and
- forming a work function layer, wherein the work function layer covers a surface of the gate dielectric layer;
- S5:
- forming a plurality of metal gates in a region where the plurality of polysilicon gates is removed, wherein the plurality of metal gates, the plurality of fins, the gate dielectric layer, and the work function layer are configured into one of a plurality of metal gate structures of the fin field-effect transistor;
- S6:
- forming a first groove by removing an edge region of ends of the plurality of metal gates that protrude from a region containing the plurality of fins, and disposing a first dielectric layer in the first groove;
- and
- S7:
- forming a zero-metal layer to connect out the source region and the drain region, wherein the source region and drain region combined with the plurality of metal gate structures are further configured into the fin field-effect transistor.