Fabrication of gate-all-around integrated circuit structures having additive metal gates

An integrated circuit structure, comprising:

• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion, wherein the second portion of the N-type conductive layer is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires;
• and
• a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the N-type conductive layer.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion, wherein the second portion of the P-type conductive layer is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires;
• and
• a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion, wherein the second portion of the N-type conductive layer is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires;
• and
• a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the N-type conductive layer.