Semiconductor device structure and methods of forming the same

A semiconductor device structure, comprising:

• a first semiconductor fin comprising a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface;
• a first gate electrode layer disposed adjacent the first, third, and fourth surfaces of the first semiconductor fin;
• a second semiconductor fin comprising a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface;
• a second gate electrode layer disposed adjacent the first, third, and fourth surfaces of the second semiconductor fin;
• a dielectric feature disposed between the first gate electrode layer and the second gate electrode layer;
• a first source/drain epitaxial feature in contact with the first semiconductor fin;
• a first inner spacer disposed between the first source/drain epitaxial feature and the first gate electrode layer, wherein the first inner spacer is in contact with the first source/drain epitaxial feature, and wherein the first inner spacer comprises a first material;
• a first spacer in contact with the first inner spacer, wherein the first spacer comprises a second material different from the first material;
• a second source/drain epitaxial feature in contact with the second semiconductor fin;
• a second inner spacer disposed between the second source/drain epitaxial feature and the second gate electrode layer, wherein the second inner spacer is in contact with the second source/drain epitaxial feature, and wherein the second inner spacer comprises the first material;
• and
• a second spacer in contact with the second inner spacer, wherein the second spacer comprises the second material.

A method for forming a semiconductor device structure, comprising:

• forming a semiconductor fin;
• forming a first spacer on the semiconductor fin;
• recessing the first spacer to form a first opening;
• forming a first sacrificial semiconductor material in the first opening;
• forming a sacrificial gate stack over a first portion of the semiconductor fin and a first portion of the first sacrificial semiconductor material, wherein a second portion of the semiconductor fin and a second portion of the first sacrificial semiconductor material are exposed;
• forming second spacers on sidewalls of the sacrificial gate stack;
• removing end portions of the sacrificial semiconductor material to form gaps;
• and
• forming inner spacers in the gaps, wherein each inner spacer is in contact with a corresponding second spacer.