Field-effect transistors (fet) circuits employing topside and backside contacts for topside and backside routing of fet power and logic signals, and related complementary metal oxide semiconductor (cmos) circuits

A method of fabricating a field-effect transistor (FET) circuit, comprising:

• forming a FET, comprising:
• forming a conduction channel above a substrate;
• forming a source disposed in a first end portion of the conduction channel, the source comprising a source top surface and a source bottom surface;
• forming a drain disposed in a second end portion of the conduction channel opposite the first end portion, the drain comprising a drain top surface and a drain bottom surface;
• and
• forming a gate disposed above at least a portion of the conduction channel and between the first end portion and the second end portion of the conduction channel, the gate comprising a gate top surface and a gate bottom surface;
• forming a topside metal contact in contact with one of the source top surface, the drain top surface, and the gate top surface;
• forming a backside metal contact in contact with one of the source bottom surface, the drain bottom surface, and the gate bottom surface;
• forming a topside metal line disposed above the gate and in electrical contact with the topside metal contact;
• forming a backside metal line disposed below the conduction channel and in electrical contact with the backside metal contact;
• forming a signaling metal line configured to carry logic signals in contact with one of the topside metal line and the backside metal line;
• and
• forming a power rail configured to carry a power signal from a power source in contact with one of the backside metal line and the topside metal line not in contact with the signaling metal line.

A complementary metal-oxide semiconductor (CMOS) circuit, comprising:

• a positive (P)-type diffusion region disposed in a substrate;
• a negative (N)-type diffusion region disposed in the substrate;
• a power rail having a first longitudinal axis disposed in a first direction;
• a signaling metal line electrically coupled to another circuit;
• a P-type field-effect transistor (FET) (PFET) formed in the N-type diffusion region, the PFET comprising:
• a P-type conduction channel;
• a P-type source disposed in a first end portion of the P-type conduction channel;
• a P-type drain disposed in a second end portion of the P-type conduction channel opposite the first end portion;
• and
• a first gate disposed above at least a portion of the P-type conduction channel and between the first end portion and the second end portion of the P-type conduction channel;
• an N-type field-effect transistor (NFET) formed in the P-type diffusion region, the NFET comprising:
• an N-type conduction channel;
• an N-type source disposed in a first end portion of the N-type conduction channel;
• an N-type drain disposed in a second end portion of the N-type conduction channel opposite the first end portion;
• and
• a second gate disposed above at least a portion of the N-type conduction channel and between the first end portion and the second end portion of the N-type conduction channel;
• a first backside metal contact in contact with one of the P-type source, the P-type drain, and the first gate;
• a second backside metal contact in contact with one of the N-type source, the N-type drain, and the second gate;
• a first backside metal line disposed below the substrate, the first backside metal line electrically coupled to the first backside metal contact;
• a second backside metal line disposed below the substrate, the second backside metal line electrically coupled to the second backside metal contact;
• the first backside metal line coupled to one of the power rail and the signaling metal line;
• and
• the second backside metal line coupled to one of the signaling metal line and the power rail not coupled to the first backside metal line.