Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates

An integrated circuit structure, comprising:

• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a gate stack over the first vertical arrangement of horizontal nanowires;
• a gate plug over the second vertical arrangement of horizontal nanowires, an end of the gate plug spaced apart from an end of the gate stack by a gap;
• and
• a dielectric structure comprising a first portion forming a gate spacer along sidewalls of the gate stack, a second portion forming a spacer along sidewalls of the gate plug, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

A method of fabricating an integrated circuit structure, the method comprising:

• forming a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires;
• forming a gate line over the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires;
• cutting the gate line to form a first gate stack over the first vertical arrangement of horizontal nanowires and a second gate stack over the second vertical arrangement of horizontal nanowires, wherein an end of the second gate stack is spaced apart from an end of the first gate stack by a gap;
• and
• forming a dielectric structure comprising a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a first gate stack over the first vertical arrangement of horizontal nanowires;
• a second gate stack over the second vertical arrangement of horizontal nanowires, an end of the second gate stack spaced apart from an end of the first gate stack by a gap;
• and
• a dielectric structure comprising a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.