Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions

A method of fabricating an integrated circuit structure, the method comprising:

• forming a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate;
• forming an intervening dielectric structure between the first vertical arrangement of nanowires and the second vertical arrangement of nanowires;
• and
• forming first epitaxial source or drain structures at ends of the first vertical arrangement of nanowires, and forming second epitaxial source or drain structures at ends of the second vertical arrangement of nanowires, ones of the second epitaxial source or drain structures and corresponding ones of the first epitaxial source or drain structures non-merged and in contact with the intervening dielectric structure.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate;
• one or more gate stacks over the first and second vertical arrangements of nanowires;
• first epitaxial source or drain structures at ends of the first vertical arrangement of nanowires;
• second epitaxial source or drain structures at ends of the second vertical arrangement of nanowires;
• and
• an intervening dielectric structure between adjacent ones of the first epitaxial source or drain structures and between adjacent ones of the second epitaxial source or drain structures.