Integrated circuit layout and method thereof

An IC structure, comprising:

• a first transistor, comprising:
• a first active region and a second active region separated by an isolation structure, wherein the first and second active regions extend along a first direction;
• a gate having a plurality of gate structures disposed on the first and second active regions, respectively, wherein along the first direction, an effective gate length of the gate is n times a critical dimension of a technology node of the first transistor, and n is a positive integer and is greater than 1;
• a plurality of gate spacers disposed adjacent each of the gate structures of the gate;
• and
• a first source/drain region in the first active region;
• and
• a second source/drain region in the second active region;
• and
• a second transistor having a gate length substantially equal to the critical dimension of the technology node of the first transistor.

A method, comprising:

• forming a first active region and a second active region over a substrate and extending along a first direction, wherein the first active region and the second active region are separated by an isolation structure;
• forming a first gate structure over first active region;
• forming a plurality of second gate structures over the second active region, wherein along the first direction, a sum of gate lengths of the second gate structures is n times a gate length of the first gate structure, and n is a positive integer and is greater than 1;
• forming first source/drain regions in the first active region;
• and
• forming second source/drain regions in the second active region, wherein portions of the second active region between two adjacent second gate structures have lower dopant concentrations than the second source/drain regions.