Resistor and resistor-transistor-logic circuit with gan structure and method of manufacturing the same
AssigneeUnited Microelectronics Corp.
InventorsKuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Te-Wei Yeh, Yi-Chun Chen
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Abstract
A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor.
Claims24
A resistor-transistor-logic circuit with GaN structures, comprising:
- a GaN layer with a high-voltage device region, a low-voltage device region and a resistor region;
- an AlGaN barrier layer on said GaN layer;
- multiple p-type doped GaN capping layers on said AlGaN barrier layer, wherein parts of said p-type doped GaN capping layers in said high-voltage device region and said low-voltage device region convert said GaN layer under said parts of said p-type doped GaN capping layers into gate depletion regions, said GaN layer not covered by said p-type doped GaN capping layers in said resistor region functions as a 2DEG resistor;
- multiple first gates, wherein each of said first gates is formed on one of said p-type doped GaN capping layers in said high-voltage device region;
- multiple first sources and first drains formed on said GaN layer in said high-voltage device region, wherein said first gates, said first sources and said first drains constitute high-voltage HEMTs;
- multiple second gates, wherein each of said second gates is formed on one of said p-type doped GaN capping layers in said low-voltage device region;
- and
- multiple second sources and second drains formed on said GaN layer in said low-voltage device region, wherein said second gates, said second sources and said second drains constitute low-voltage logic FETs.
A resistor with GaN structures, comprising:
- a GaN layer with a 2DEG resistor region and an undoped polysilicon resistor region;
- an AlGaN barrier layer on said GaN layer in said 2DEG resistor region;
- multiple p-type doped GaN capping layers arranged on said AlGaN barrier layer so that said GaN layer not covered by said p-type doped GaN capping layers in said 2DEG resistor region is converted into a 2DEG resistor;
- a passivation layer on said GaN layer;
- and
- an undoped polysilicon layer on said passivation layer in said undoped polysilicon resistor region and functions as an undoped polysilicon resistor.
A method of manufacturing a resistor-transistor-logic circuit with GaN structures, comprising:
- providing a substrate with a high-voltage device region, a low-voltage device region and a resistor region;
- sequentially forming a GaN layer, an AlGaN barrier layer and a p-type doped GaN capping layer on said substrate;
- patterning said p-type doped GaN capping layer into multiple p-type doped GaN capping patterns, wherein said GaN layer under parts of said p-type doped GaN capping patterns is converted into gate depletion regions, and said GaN layer not covered by said p-type doped GaN capping patterns in said resistor region functions as 2DEG resistors;
- forming a passivation layer on said GaN layer and said p-type doped GaN capping patterns;
- forming multiple sources and drains on said GaN layer in said passivation layer;
- and
- forming multiple gates on said p-type doped GaN capping patterns in said passivation layer, wherein said gates, said sources and said drains in said high-voltage device region constitute high-voltage HEMTs, and said gates, said sources and said drains in said low-voltage device region constitute low-voltage logic FETs.
Dependencies are inferred from the claim text.