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US 2022/0093582 A1Published application
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorYounglyong Kim
Life of this patent
Estimating the term…
Abstract
Disclosed is a semiconductor package including a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and laterally spaced apart from the first semiconductor chip, a dummy chip on the first semiconductor chip, and a dielectric layer between the first semiconductor chip and the dummy chip. A top surface of the first semiconductor chip may be lower than a top surface of the second semiconductor chip. The dielectric layer may include an inorganic dielectric material.
Claims20
A semiconductor package, comprising:
- a substrate;
- a first semiconductor chip on the substrate;
- the first semiconductor chip including a plurality of first chip pads adjacent to a top surface of the first semiconductor chip;
- a second semiconductor chip on the substrate, the second semiconductor chip laterally spaced apart from the first semiconductor chip;
- and
- an upper semiconductor chip on the first semiconductor chip,
- a bottom surface of the upper semiconductor chip facing the top surface of the first semiconductor chip,
- the upper surface of the upper semiconductor chip facing the top surface of the first semiconductor chip,
- the upper semiconductor chip including a plurality of second chip pads adjacent to the bottom surface of the upper semiconductor chip,
- the plurality of second chip pads be in a directly connected to the plurality of first chip pads, and
- the second semiconductor chip arranged so the top surface of the first semiconductor chip is lower than a top surface of the second semiconductor chip.
8 more elements
A semiconductor package, comprising:
- a substrate;
- a first semiconductor chip on the substrate;
- second semiconductor chips on the substrate, the second semiconductor chips laterally spaced apart from the first semiconductor chip and the first semiconductor chip disposed between the second semiconductor chips;
- and
- an upper semiconductor chip on the first semiconductor chip,
- wherein a thickness of the first semiconductor chip is less than a thickness of each of the second semiconductor chips,
- wherein the first semiconductor chip includes a plurality of first chip pads adjacent to a top surface of the first semiconductor chip, the upper semiconductor chip includes a plurality of second chip pads adjacent to a bottom surface of the upper semiconductor chip, and the bottom surface of the upper semiconductor chip faces with the top surface of the first semiconductor chip, and
- wherein the plurality of second chip pads are directly connected to the plurality of first chip pads.
5 more elements
Dependencies are inferred from the claim text.