US 2022/0093573 A1Published application

Semiconductor module

AssigneeInfineon Technologies Austria AG

InventorsAngela Kessler, Josef Hoeglauer, Gerhard Noebauer

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Abstract

A semiconductor module includes a laminate structure having an electrically insulating core layer with opposing first and second sides, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side. First and second transistor devices are coupled to form a half-bridge circuit. Both transistor devices have a first side at which a cell field is arranged and an opposing second side. A control chip has a first side with contact pads. The transistor devices and control chip are arranged laterally adjacent one another and embedded in the core layer. The first side of the control chip and one transistor device and the second side of the other transistor device face towards the first redistribution layer on the first side of the core layer.

Claims18

Dependent claims

A semiconductor module, comprising:

a laminate structure comprising an electrically insulating core layer having a first side and a second side opposing the first side, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side of the core layer;
a first transistor device and a second transistor device coupled to form a half-bridge circuit, wherein the first transistor device has a first side at which a cell field is arranged and a second side opposing the first side, and the second transistor device has a first side at which a cell field is arranged and a second side opposing the first side;
and
a control chip having a first side with contact pads;
wherein the first transistor device, the second transistor device and the control chip are arranged laterally adjacent one another and embedded in the core layer,
wherein the first side of the control chip, the first side of one of the first and second transistor devices and the second side of the other one of the first and second transistor devices face towards the first redistribution layer on the first side of the core layer.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/480,611Filed 21 Sep 2021
Priority: EP 20198168.524 Sep 2020
Published: 24 Mar 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10W 70/60
Package substrates; Interposers; Redistribution layers [RDL]: insulating or insulated package substrates; Interposers; Redistribution layers
H10W 90/00
Package configurations
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 70/611
Insulating or insulated package substrates; Interposers; Redistribution layers: for connecting multiple chips together