Backside contact for thermal displacement in a multi-wafer stacked integrated circuit

A method of forming an integrated circuit, the method comprising:

• forming a semiconductor device on a frontside of a semiconductor substrate;
• forming an interconnect structure over the semiconductor device;
• forming a dielectric layer over a backside of the semiconductor substrate;
• patterning the dielectric layer to form a first opening in the dielectric layer, wherein the first opening exposes a surface of the backside of the semiconductor substrate;
• forming a glue layer having a first thickness over the first opening;
• filling the first opening with a first material to form a backside contact that is separated from the semiconductor substrate by the glue layer;
• forming a second opening that defines a conical gap through the semiconductor substrate, wherein the second opening extends into the interconnect structure;
• forming a lining in the second opening, wherein the lining comprises a chemical barrier layer and an electrical insulator layer and the lining is thicker than the glue layer;
• filling the second opening with a second material to form a through substrate via (TSV), wherein the lining separates the TSV from the semiconductor substrate;
• and
• forming a bonding structure on the backside of the dielectric layer, wherein the backside contact is coupled to the bonding structure and the TSV.

A method of forming an integrated circuit, the method comprising:

• forming a dielectric layer over a backside of a semiconductor substrate;
• patterning the dielectric layer to form a first opening in the dielectric layer, wherein the first opening exposes a surface of the backside of the semiconductor substrate;
• forming a glue layer over the first opening;
• filling the first opening with a first material to form a backside contact that is separated from the semiconductor substrate by the glue layer;
• forming a second opening in the dielectric layer, wherein the second opening extends through the semiconductor substrate;
• forming a lining in the second opening using a second material, wherein the lining comprises a chemical barrier layer and an electrical insulator;
• and
• filling the second opening with a third material to form a through substrate via (TSV), wherein the lining separates the TSV from the semiconductor substrate and where a top surface of the backside contact extends past a highest lower surface of the TSV.