Semiconductor device and method for fabricating thereof

A semiconductor device comprising:

• a plurality of semiconductor patterns spaced apart in a first direction;
• a plurality of mold insulating layers between the plurality of semiconductor patterns;
• a plurality of silicide patterns contacting the plurality of semiconductor patterns;
• a plurality of side extension holes defined by the plurality of silicide patterns and adjacent mold insulating layers, of the plurality of mold insulating layers that are adjacent to each other in the first direction, the plurality of side extension holes extending in a second direction perpendicular to the first direction;
• and
• a plurality of first metal conductive films in the plurality of side extension holes, the plurality of first metal conductive films connected to the plurality of silicide patterns,
• wherein each of the silicide patterns includes a first sidewall facing a semiconductor pattern of the plurality of semiconductor patterns, and a second sidewall facing a first metal conductive film of the plurality first metal conductive films,
• each of the side extension hole includes an upper face and a lower face defined by the adjacent mold insulating layers, and a sidewall defined by the second sidewall of the silicide pattern,
• in each of the extension holes on the side surface, a ratio of a width of the side extension hole in the second direction to a height of the side extension hole in the first direction is 5 or more, and
• the widths of each of the silicide patterns in the second direction are the same at corresponding heights.

A semiconductor device comprising:

• a plurality of mold insulating layers spaced apart in a first direction;
• a plurality of semiconductor patterns between the plurality of mold insulating layers;
• a plurality of gate electrodes on the plurality of semiconductor patterns, the plurality of gate electrodes extending in a second direction perpendicular to the first direction;
• a bit line extending in the first direction and connected to the plurality of semiconductor patterns;
• a plurality of silicide patterns contacting the plurality of semiconductor patterns;
• a plurality of side extension holes defined by the plurality of silicide patterns and adjacent mold insulating layers of the plurality of mold insulating layers, the plurality of side extension holes extending in a third direction perpendicular to the first direction and the second direction;
• and
• a plurality of capacitors the plurality of side extension holes and connected to the plurality of silicide patterns,
• wherein each side extension hole includes an upper face and a lower face defined by the adjacent mold insulating layers and a sidewall defined by a silicide pattern of the plurality of silicide patterns,
• each of the silicide patterns does not extend along the upper face of the side extension hole and the lower face of the side extension hole, and
• widths of each of the silicide patterns in the third direction are the same at points corresponding heights.